In memories, particularly dynamic random access memories (DRAMs), data and address signals on lines running from one end of a semiconductor chip to another are subject to severe delays in transit along the lines. Such delays are caused by parasitic loading attributed to distributed impedances associated with the lines.
FIG. 1a illustrates a schematic drawing of a conventional driver-to-receiver bus communication scheme. Driver circuit 2, including inverter 4, receives an input signal from input node IN. Driver circuit 2 can, for instance, represent a tri-state driver. Node DOUT at the output of driver circuit 2 is connected to node A, at the input of receiver circuit 6, by line 8 which carries distributed impedances, including distributed resistance, inductance and capacitance. Receiver circuit 6 can, for instance represent a cascoded sensing amplifier.
FIG. 1b illustrates a timing diagram for the circuit of FIG. 1a. As shown, for a transition at node IN from a logic high to a logic low, a transition at node END follows after a delay of time t.sub.a. Additionally note that a change in node A, shown in FIG. 1a going from logic low to logic high, takes even longer time t.sub.a. Delay time, t.sub.a or longer, adversely affects memory operation in that memory speed is slowed as a result thereof.
This may be particularly true with high density memories, i.e., those of 16 megabit or greater in size.
FIGS. 1c and 1d represent a schematic drawing of a conventional driver-to-receiver communication bus scheme and its associated timing diagram, respectively, of complemented signals (indicated by the bar succeeding the label) of their counterparts shown in FIGS. 1a and 1b.